1. Field of the Invention
The present invention relates to a voltage dropping power unit adapted to drop an internal supply voltage of semiconductor memory device-mounted information processing equipment such as a personal computer and to supply a predetermined operating voltage obtained by dropping the internal supply voltage to a semiconductor memory device such as a RAM (Random Access Memory) or a like mounted on the information processing equipment and more particularly to the voltage dropping power unit capable of reducing power consumption in the voltage dropping power unit itself while the semiconductor memory device is placed in a quiescent state.
2. Description of the Related Art
Generally, in a section on which a semiconductor memory device is packaged is embedded a voltage dropping power unit used to supply an operating voltage obtained by dropping an internal supply voltage of semiconductor memory device-based information processing equipment to a semiconductor memory device. That is, the internal supply voltage is dropped by the voltage dropping power unit and a dropped voltage is applied as the operating voltage to the semiconductor memory device including a memory array or a like.
As shown in FIG. 6, a conventional voltage-dropping power unit 1 is provided with a voltage control circuit 2 having an active element 5 adapted to generate, using a supply voltage Vcc, a dropped voltage Vdd obtained by being controlled depending on a control voltage, a reference circuit 3 composed of an active element for calibrating currents 6 and voltage-dividing resistors 7a and 7b making up a group of voltage-dividing resistors and adapted to produce a predetermined reference voltage to be set by the active element 6 and a differential circuit 4 adapted to receive the reference voltage from the reference circuit 3 as an input voltage and an output voltage from the voltage control circuit 2 as an input voltage and to feed the control voltage to the voltage control circuit 2 so that both the input voltages are made equal. The reference circuit 3 outputs a voltage which has dropped at a node A when currents have flowed through the group of the voltage-dividing resistors, as the reference voltage, to the differential circuit 4. The differential circuit 4 is a so-called current mirror amplifying circuit which is provided with a current path composed of an active element 8a to receive a supply voltage Vcc and of an active element 9a connected in serial to the active element 8a to receive the dropped voltage Vdd being fed back from the voltage control circuit 2 and with a current path composed of an active element 8b to connect to a terminal of a supply voltage Vcc and of an active element 9b connected in serial to the active element 8b to receive the reference voltage and adapted to take out the control voltage based on a potential at a node B connected between the active element 8b and the active element 9b. Currents flowing through both the current paths can be adjusted by an active element for adjusting sensitivity 10. A voltage taken out from a node C between the active element 9a and the active element 8a is fed to the active element 9a and to the active element 9b to be used as the control voltage.
The differential circuit 4 performs a differential operation so that currents flowing through both the current paths are made equal and therefore the output voltage from the voltage control circuit 2 is made equal to the reference voltage, thus enabling the output voltage from the voltage control circuit 2, that is, the dropped voltage Vdd to be held at a constant value.
However, while the semiconductor memory device is placed in a quiescent state, the conventional voltage-dropping power unit continues to operate even when the semiconductor memory device is placed in operation. That is, in FIG. 6, in the reference circuit 3, constant currents flow, irrespective of whether the semiconductor memory device is in operation or in quiescent operation, through the active element for calibrating current 6 and the group of the voltage dividing resistors and the reference circuit 3 continues to output the predetermined reference voltage to the differential circuit 4. Moreover, in the differential circuit 4 which receives the reference voltage, currents continue to flow through the current path composed of the active elements 8a and 9a and through the current path composed of the active elements 8b and 9b and then through the active element 10 for adjusting sensitivity. As a result, even when the semiconductor memory device is in a quiescent state, power is consumed in the voltage dropping power unit in the same manner as in the case of in the semiconductor memory device being in operation.
In view of the above, it is an object of the present invention to provide a voltage dropping power unit being capable of reducing power consumption in the voltage dropping power unit while a semiconductor memory device is placed in a quiescent state.
According to a first aspect of the present invention, there is provided a voltage dropping power unit for dropping a supply voltage and for applying a dropped voltage to a semiconductor memory device, including:
a voltage control circuit to produce a voltage to be controlled depending on a control voltage in order to supply an operating voltage to the semiconductor memory device;
a reference voltage generating circuit to generate a reference voltage used to produce the control voltage;
a voltage differential circuit to perform a differential operation so that the voltage output from the voltage control circuit is made equal to the reference voltage irrespective of a level of said voltage output from the voltage control circuit; and
wherein the reference voltage generating circuit is provided with a voltage dividing resistor to generate the reference voltage by receiving a current from a supply voltage source and a switching device to form a short-circuit across the voltage dividing resistor in order to decrease an operating current flowing through the voltage differential circuit while the semiconductor memory device is placed in a quiescent state.
In the foregoing, a preferable mode is one wherein the switching device in the reference voltage generating circuit is provided with a transistor device operated to form the short-circuit when the semiconductor memory device is in quiescent operation.
Also, a preferable mode is one wherein the reference voltage generating circuit includes an active device connected in serial to the voltage dividing resistor to adjust an amount of a current flowing through the voltage dividing resistor for making the reference voltage adjustable.
Also, a preferable mode is one wherein the transistor device is an n-type MOS (Metal Oxide Semiconductor) transistor used to receive a signal informing a quiescent operation of the semiconductor memory device.
Also, a preferable mode is one wherein the signal informing a quiescent operation of the semiconductor memory device is a negative logical signal and wherein the n-type MOS transistor receives the signal as an inverted signal through an inverter.
Also, a preferable mode is one wherein the MOS transistor and the voltage dividing resistor are connected in parallel and wherein the voltage dividing resistor is short-circuited when the inverted signal is fed to the MOS transistor.
Also, a preferable mode is one wherein the differential circuit is provided with a pair of MOS transistors being connected in parallel with each other and each having a gate and wherein the gate of one of said MOS transistors acts as an input terminal to receive a reference voltage from the reference voltage generating circuit and the gate of the other of the MOS transistors acts as an input terminal to receive an output voltage from the voltage control circuit.
Also, a preferable mode is one wherein the one MOS transistor making up the pair of MOS transistors is an n-type MOS transistor and wherein the switching device in the reference voltage generating circuit, while the semiconductor memory device is in quiescent operation, forms a short-circuit across the voltage dividing resistor in order to reduce the reference voltage to be applied to the gate of the n-MOS transistor.
According to a second aspect of the present invention, there is provided a voltage dropping power unit for dropping a supply voltage and for applying a dropped voltage to a semiconductor memory device, including:
a voltage control circuit to produce a voltage to be controlled depending on a control voltage in order to supply an operating voltage to the semiconductor memory device;
a reference voltage generating circuit to generate a reference voltage used to produce the control voltage;
a voltage differential circuit to perform a differential operation so that the voltage output from the voltage control circuit is made equal to the reference voltage irrespective of a level of the voltage output from said voltage control circuit; and
wherein the reference voltage generating circuit is provided with a voltage dividing resistor to produce the reference voltage by receiving a current from a supply voltage source and a first switching device to interrupt a current to the voltage dividing resistor while the semiconductor memory device is in quiescent operation and wherein the voltage differential circuit is provided with a switching circuit used to switch on or off a differential operating current, which is operated to interrupt the operating current while the semiconductor memory device is placed in a quiescent state.
In the foregoing, a preferable mode is one wherein the switching circuit has an active element operated to increase or decrease the operating current for calibrating sensitivity of differential operations of the differential circuit while the semiconductor memory device is in operation and operated to interrupt the operating current while the semiconductor memory device is in quiescent operation and a control section used to control the operations of the active element.
Also, a preferable mode is one wherein the active element is a MOS transistor to increase or decrease operating currents depending on a signal fed to a gate of the MOS transistor and wherein the control section includes a switching mechanism operated to allow an instruction signal having an adjustable voltage value to be fed to the gate of the transistor while the semiconductor memory device is in operation and not to allow the signal to be fed to the gate while the semiconductor memory device is in quiescent operation and a second switching device to apply a voltage required to activate the MOS transistor to the gate of said MOS in order to interrupt the operating current while the semiconductor memory device is in quiescent operation.
Also, a preferable mode is one wherein the switching mechanism is provided with a CMOS (Complementary MOS) circuit in which complementary MOS transistors are connected in parallel and a gate of each of the complementary MOS transistor receives each of complementary control signals.
Also, a preferable mode is one wherein the voltage control circuit has a first active element to supply a voltage to be controlled by the control voltage to the semi conductor memory device and wherein the voltage differential circuit has a second switching device to supply a control voltage for interrupting the first active element to the active element while the semiconductor memory device is in quiescent operation.
Also, a preferable mode is one wherein the first switching device included in said reference voltage generating circuit is provided with a transistor operated to interrupt currents to be supplied to the voltage dividing resistor when the transistor receives a signal informing a quiescent operation of the semiconductor memory device.
Also, a preferable mode is one wherein the voltage control circuit has a second active element being connected in parallel with the first active element to supply a predetermined constant voltage to the semiconductor memory device while the semiconductor memory device is in quiescent operation.
Also, a preferable mode is one wherein the second active element consists of a transistor operated to supply a predetermined constant voltage to the semiconductor memory device when the transistor receives a signal informing a quiescent operation of the semiconductor memory device.
Also, a preferable mode is one wherein the voltage control circuit has a second active element being connected in serial to an output terminal of the first active element in order to supply a predetermined constant voltage to the semiconductor memory device while the semiconductor memory device is in quiescent operation.
Also, a preferable mode is one wherein the second active element consists of a transistor device operated to supply a ground voltage to the semiconductor memory device when the transistor receives a signal informing a quiescent operation of the semiconductor memory device.
Furthermore, a preferable mode is one wherein the voltage control circuit includes a third active element used to supply a voltage to be controlled depending on the control voltage to the semiconductor memory device and a fourth active element being connected in serial to an output terminal of the third active element used to output a voltage being different from an output voltage from the second active element and being equal to a ground voltage when the fourth active element receives a signal informing a quiescent operation of the semi conductor memory device.